1. Field of the Invention
The present disclosure relates to a low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC) and a conversion method using the same. More particularly, the present disclosure relates to a low-power, high-speed SAR ADC and a conversion method using the same capable of improving a sampling speed.
2. Discussion of Related Art
In data processing, digital signal processing having a high processing speed and insensitive to environment noise is more advantageous than analog signal processing. However, because many signals in the nature have an analog form, it is necessary to convert an analog signal input in an integrated circuit into a digital signal.
ADCs may be roughly classified into a pipeline ADC, an SAR ADC, a flash ADC, and a delta-sigma ADC. According to a sampling speed and resolution, there is a suitable structure.
Among the ADCs, the SAR ADC advantageously has a simpler circuit structure than ADCs of different structures and is operable at low power, but has a disadvantage of a low operation speed. However, the operation speed is improved by applying time interleaved technology. Accordingly, because the SAR ADC using the time interleaved technology is more advantageous than other existing structures in terms of low power and has a high-speed operation, the SAR ADC is known as an optimized structure in terms of power consumption and an operation speed.
However, because this SAR ADC converts an analog signal into a digital signal through comparison and approximation processes in many steps, a sum of a clock cycle time for a number of comparison-approximation processes and a time of one clock cycle for sampling an analog signal is required. For example, in the case of the SAR ADC having the resolution of N bits, a time taken to convert all data is a total time of (N+1) clock cycles obtained by adding a time of N clock cycles for N comparisons and a time of one clock cycle for the above-described sampling. That is, a sampling speed of the conventional SAR ADC is limited due to a limit of an internal clock speed as described above.
On the other hand, an detect and skip (DAS) algorithm using coarse and fine DACs has been proposed to reduce switching power of a capacitor type DAC, but the DAS algorithm has a sampling speed of about 10 KS/s and is not suitable for the high-speed SAR ADC.